BMS: Battery Management System, any system that manages a rechargeable battery and protects it from operating outside of safe conditions
BMU: Battery Management Unit, alternative term for a BMS
BOM: Bill of materials. A list of all the parts (including optional components) in a product
Boost: Takes input voltage and increases it
Bottom-half handler: In a two-stage interrupt handling software architecture, the bottom-half handler is an interrupt handler that runs in user mode (normal operating context) and is invoed by a top-half handler.
The top-half handler runs in an interrupt context and is responsible for interacting with the hardware, clearing the interrupt, and scheduling bottom-half handlers to run outside of the interrupt context
All interrupts and normal operating system features are available when bottom-half handlers are run
Bottom-half handlers are often executed by a high-priority interrupt thread, which maintains a queue of bottom-half handlers to execute
Bottom-half handlers perform the intensive work related to an interrupt, such as processing data and invoking other functions
BSP: Board support package. A software layer containing hardware-specific drivers and other code.
COGS: Cost of goods sold. The total amount of money spent to produce the inventory divided by the number of units in inventory. COGS includes assembly, freight, logistics, duties, marketing, etc.
Hardware: a physical entity of a larger system, such as a chip on a circuit board
Software: a module in modular systems
For component that is part of a component-based arch:
A component is a self-contained, usually concurrent, object with a well-defined interface, capable of being used in different applications from that for which it was originally designed. In distributed applications, a component is a basic unit of deployment and distribution.
Cortex-A: ARM processor family. Application processors with increased capabilities, typically able to run a full operating system such as Linux.
Cortex-M: ARM processor family. Smallest and lowest power processors available by ARM.
With manufacturing, cycle time can be reported for each stage of the manufacturing process or for the overall time a unit spends on the production line
DBMS: Database management system
DCM: Data collection module
DDD: Domain driven design
Descriptor: An abstract identifier used to access a file, socket, or other system resource.
DFM: Design for manufacturing
The process of optimizing a design so that it can be produced at scale without problems
Process for ensuring consistency and quality during manufacturing
DFC: Design for cost
DFU: Device Firmware Upgrade
Generally: The mode for USB products where there is no firmware or software on the device, before any install OR it thinks there is no software (erased device)
USB Specific: a vendor- and device-independent mechanism for upgrading the firmware of USB devices with improved versions provided by their manufacturers, offering (for example) a way for firmware bugfixes to be deployed.
DFV: Design for variability
DFX: Design-for-X, Design for Excellence (Microsoft)
X can be any generic trait or attribute which the team is designing for
DoDAF: Department of Defense Architecture Framework
DRI: Directly responsible individual
DSM: Dependency structure matrix
DSP: Digital signal processor
DVM: Digital voltmeter
dynamic shared library, dynamic library, DLL: A binary executable that is loaded dynamically into an application’s process space rather than linked statically as part of the application binary.
DIP: Dual In-line Package
DOA: Dead-on-arrival. Usually refers to new software versions not working or new boards having a flaw. This flaw is often catastrophic and renders the software/hardware unusable.
DOE: Design of experiments. Commonly used to mean "experiment"
DMM: Digital Multi-meter
DQ / DQ'd: Disqualify or disqualified
DSP: Digital signal processor
DUT: Device under test
DVT: Design validation & Test (production stage)
Used to validate that the production process can build units of sufficient quality
Units should match final design - no major design changes should be anticipated at the start of DVT.
IMU: Inertial Measurement Unit. Accelerometer, gyroscope, etc.
IO, I/O: Input/output.
IoT: Internet of things
IP: Intellectual property, Internet Protocol
IP core, IP block: A semiconductor intellectual property core. A reusable unit of logic, cell, or integrated circuit layout design that is the intellectual property of one party. Other designers will licenses these blocks for use in their own chips.
IPC: Inter-process communication
ISA: Instruction-set architecture
ISO: International Organization for Standardization
ISP: Image signal processor, in-system programming
IQ: Image quality
IQC: Incoming quality control
LMA: Load memory address
Every loadable or allocatable output section in a binary has two addresses: VMA and LMA (load memory address)
The VMA is the address the section will have when the output file is run
The LMA is the address to which the section will be loaded
In many cases, VMA and LMA are the same
An example of when the VMA and LMA might be different is when XIP mode is enabled
The data section is loaded into ROM during the flashing process
When the program starts, the data section is copied into RAM
In this case the ROM address would be the LMA, and the RAM address would be the VMA
LOC: Lines of code
LOE: Level of effort
Looks-like Prototype: A cosmetically-focused prototype which looks like the intended product design, but does not support functional operation.
Loopers: Units that enter into the repair/return cycle repeatedly
LSB: Least significant bit
LT, L/T: Lead-time. How long it takes to get a part made/shipped.
LTV: Lifetime value of a customer. Total profit made from a customer, including hardware, software subscriptions, and other revenue sources. Also referred to as "CLV"
LUT: Look-up table
LVDS: Low-voltage differential signaling. When used in the context of hardware displays, it refers to FPD-Link, a hardware standard for communicating with displays.
Media access control (address). Refers to a unique identifier for a network interface controller (NIC), such as an Ethernet, Wi-Fi, or Bluetooth controller
PE: Process Engineer (Mfg), Principle Engineer (Engineering)
PFOL: Product first offline. Review first production units onsite at company location.
PHY: Indicates a "physical" layer, or the actual electrical connection and encoding hardware of a communication protocol
PLL: Phase-locked loop
PLM: Project lifecycle management. The process of managing the entire lifecycle of a product from inception, through engineering design and manufacture, to service and disposal of manufactured products.
PM: Program/project manager
PMBus: Power Management Bus
PMIC: Power management IC
PMU: Power management unit
PO: Purchase order
Typically less refined than a "prototype", used for validating a problem
Often assembled with off-the-shelf parts
POSIX: Portable Operating System Interface
PN, P/N: Part number
PNP: A type of bipolar junction transistor consisting of a layer of N-doped semiconductor between two-layers of P-doped material
Post-snap: After a form factor unit has been completely closed - assembly is finished.
PRD: Product requirements document
PRQ: Post ramp qualification. A controlled production run done during MP (after ramp) to validate a change prior to converting full production to the new design. Often done to validate new part versions or alternate sources.
Scrap Rate: The percentage of units that must be thrown away due to defects. Also known as "fallout"
SDHC: SD (as in SD card) High Capacity
SDIO: Secure digital input/output. Electronics communication bus.
SDL: Specification and Description Language
SDXC: SD (as in SD Card) Extended Capability
semaphore: A protected variable that restricts access to a shared resource
Mutexes and conditions are both different types of semaphore.
SERDES: Serializer/Deserializer. A pair of functional blocks commonly used in high-speed communications to compensate for limited input/output. These blocks convert data between serial data and parallel interfaces in each direction.
SFC: Shop floor control
SFR: Special function register - provides an interface to core and peripheral hardware functionality of a microprocessor or microcontroller. They are commonly mapped into the processor’s address space, similar to RAM
SHA: Secure hash algorithms. A family of cryptographic hash functions that are commonly used in computer systems.
SHARK: Sharing and Reusing Architectural Knowledge
SIMD: Single-instruction, multiple data
SIP: System-in-a-package. A number of integrated circuits enclosed in a single module (package)
SKU: Stock Keeping Unit
Identifies unique products - each configuration (revision, color option, size option) will have a unique SKU
Internally generated part numbers used to keep track of inventory/sales.
SLA: Service-level agreement
SMA: Surface mount assembly. Refers to putting parts on a PCB. After SMA, a PCB is referred to as a PCBA.
SMT: Surface mount technology. Also refers to the SMA + board testing process as a whole.
SN, S/N: Serial Number
SOA: Service-oriented architecture
SoC: System-on-a-chip. A complex processor with peripheral devices included in a single chip package
SOF: Cameras - Start of Frame
SOM: System-on-module. A board-level circuit that integrates a system function in a single module.
SOUP: Software of Unknown Pedigree
SPE: Secure processing environment, an ARM concept
SPI: Serial peripheral interface [communication bus], Software Process Improvement
SPL: Software Product Line
SRP: Stack resource policy, a scheduler implementation
Stakeholder: Someone who has a vested interest in the topic at hand (business, architecture, design, program)
Target Hardware Bottleneck: A common experience for embedded developers, especially with regards to concurrent hardware and software development. Refers to any one of these common time-wasters:
Target hardware is not ready, delaying software testing
Target hardware is expensive, making it difficult for developers to test on the target hardware
Target hardware is scarce, making it difficult for developers to test on the target hardware
Bugs on target hardware and untested target software leading to long periods of debugging
Long build times
Long flashing/loading times
Difficulty debugging on target hardware
T/C: Thermal cycling
TDD: Test-driven development
TEE: Trusted execution environment (ARM concept)
Tier 1/2/3 CMs: A ranking of CMs by annual revenue (not quality):
Tier 1: $1B+
Tier 2: $200M - $1B
Tier 3: $10M-200M
Tier 1/2/3 Supplier : Suppliers are ranked by their hierarchy in the chain. Tier 1 suppliers provide full assemblies, and purchase sub-assemblies from Tier 2 suppliers, who purchase components and raw materials from Tier 3 suppliers.
TIL: Test issues list
Thermocouple: An electronic component used to sense temperature
Throughput Yield: the probability that any unit will make it through the entire manufacturing process without failing. Calculated by multiplying the first-pass yield of each stage
TLCD: Top-level Context Diagram
TOGAF: The Open Group Architecture Framework
Hardware: large metal molds used for mass-producing injection molded plastic or stamped metal parts
Software: programs that support development, such as debuggers, build tools, analyzers, linters
Top-half Handler: In a two-stage interrupt handling software architecture, the top-half handler is the interrupt handler that is invoked when the hardware interrupt occurs
The top-half handler is responsible for interacting with the hardware and clearing the interrupt
The top-half handler operates in the interrupt context, and many software features may not be available, especially those that require mutexes or other OS constructs.
The top-half handler schedules/queues any number of bottom-half handlers which operate in the normal program (user mode) context and can use all software features.
Tri-state (logic): Most modern GPIO lines are implemented as a tri-state buffer. This means that the GPIO line can effectively assume three values: logical 0 (connection to ground), logical 1 (connectin to VCC), and High-impedance (also called "floating", "Hi-Z", "tri-stated")
In a manufacturing context, units that have not cleared a test stage or cleared the test line can be considered WIP
WLP: Wafer-level packaging.
Works-like Prototype: A prototype which works like the intended product (at least in some critical aspects) but does not match the intended cosmetic design
WS: Working sample. AKA Prototype
XIP: Execute-in-place. Referes to the capability for a processor to run a program directly from ROM (such as Flash). Processors without XIP capability must copy the entire program to memory before it can run.
XML: Extensible Markup Language
XP: Extreme Programming, a style of development
Yield: Percentage of units which successfully make it through the manufacturing process and can be sold to customers